2015.11.4

     

一位元

二位元

module top7;

  integer ia0, ia1, ib0, ib1, is;

  reg  a0, a1, b0, b1, s;

  wire out1, out2;

  mux_behavioral mux1(out1, out2, a0, a1, b0, b1, s);

  initial

    begin

      for (is=0; is<=1; is = is+1)

        begin

          s = is;

          for (ia0=0; ia0<=1; ia0 = ia0 + 1)

            begin

              a0 = ia0;

              for (ia1=0; ia1<=1; ia1 = ia1 + 1)

               begin

                 a1 = ia1;

for (ib0=0; ib0<=1; ib0 = ib0 + 1)

              begin

                  b0 = ib0;

for (ib1=0; ib1<=1; ib1 = ib1 + 1)

                 begin

                   b1 = ib1;

                 #20 $display("a0=%d a1=%d b0=%d b1=%d s=%d out1=%d out2=%d",a0,a1,b0,b1,s,out1,out2);

               end

            end

        end

     end

  end

end

endmodule

module mux_behavioral(OUT1, OUT2, A0, A1, B0, B1, SEL);

 output OUT1,OUT2;

 input A0, A1, B0, B1, SEL;

 wire  A0, A1, B0, B1, SEL;

 reg    OUT1, OUT2;

  always @(A0 or A1 or B0 or B1 or SEL)

   OUT1 = (A0 & ~SEL)|(B0 & SEL );

   OUT2 = (A1 & ~SEL)|(B1 & SEL );

endmodule