4位元多工器(and/or/not)
4位元(and/or/not)-程式碼
2位元(1位元+1位元)
二位元程式碼(一位元+一位元)
三位元(1位元+1位元+1位元)
三位元程式碼(1位元+1位元+1位元)
四位元(2+2)
四位元程式碼(2+2)
module HW6;
wire [3:0] A, B, OUT;
wire SEL;
system_clock #25600 clock1(SEL);
system_clock #12800 clock2(A[3]);
system_clock #6400 clock3(A[2]);
system_clock #3200 clock4(A[1]);
system_clock #1600 clock5(A[0]);
system_clock #800 clock6(B[3]);
system_clock #400 clock7(B[2]);
system_clock #200 clock8(B[1]);
system_clock #100 clock9(B[0]);
mux2 mux_1(OUT[3:2], A[3:2], B[3:2], SEL);
mux2 mux_0(OUT[1:0], A[1;0], B[1:0], SEL);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>30000)$stop;
endmodule
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule
三位元(1+2位元)
三位元程式碼(1+2位元)
module HW6;
wire [2:0] A, B, OUT;
wire SEL;
system_clock #6400 clock1(SEL);
system_clock #3200 clock2(A[2]);
system_clock #1600 clock3(A[1]);
system_clock #800 clock4(A[0]);
system_clock #400 clock5(B[2]);
system_clock #200 clock6(B[1]);
system_clock #100 clock7(B[0]);
mux mux_1(OUT[2], A[2], B[2], SEL);
mux2 mux_0(OUT[1:0], A[1;0], B[1:0], SEL);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>30000)$stop;
endmodule
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule
