2015.12.2

1

module top1; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not S1(a, A);

not S2(b, B);

not S3(c, C);

not S4(d, D);

and C1(F4, A ,c , d);

and C2(F2, a, b, D);

and C3(F3, B, c, d);

and C4(F1, C, D); 

or o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

2

module top2; 

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nor S1(a, A, A);

nor S2(b, B, B);

nor S3(c, C, C);

nor S4(d, D, D);

nor C1(F4, a ,C , D);

nor C2(F2, A, B, d);

nor C3(F3, b, C, D);

nor C4(F1, c, d); 

nor o1(NF, F4, F2, F3, F1);

nor o2(F, NF, NF);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

3

module top3; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, B);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F4, A ,c , d);

nand C2(F2, a, b, D);

nand C3(F3, B, c, d);

nand C4(F1, C, D); 

nand o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

2015.11.25

三位元行結構模式

module adder1(cout, sum, A, B, cin);

 wire x,y,z;

 output cout, sum;

 input A,B,cin;

 xor x1(x, A, B);

 xor x2(sum,x,cin);

 and a1(y, A, B);

 and a2(z, cin, x);

 xor  o1(cout, y, z);

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

adder1 a1(sum[0], c[1], a[0], b[0], c_in) ;

adder1 a2(sum[1], c[2], a[1], b[1], c[1]) ;

adder1 a3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

module adder1(cout, sum, A, B, cin);

 wire x,y,z;

 output cout, sum;

 input A,B,cin;

 xor x1(x, A, B);

 xor x2(sum,x,cin);

 and a1(y, A, B);

 and a2(z, cin, x);

 xor  o1(cout, y, z);

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

adder1 a1(sum[0], c[1], a[0], b[0], c_in) ;

adder1 a2(sum[1], c[2], a[1], b[1], c[1]) ;

adder1 a3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

2015.11.18

一位元全加法器.行為模式

module test_adder1;

 reg a,b;

 reg carry_in;

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial

  begin

    carry_in = 0; a = 0; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 0)

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 0+1+0=01 sum is WRONG!");

              else

               $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 0)

               $display(" 0+1+1=10 sum is WRONG!");

              else

               $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 1+0+0=01 sum is WRONG!");

              else

               $display(" 1+0+0=01 sum is RIGHT!");

    carry_in = 1; a = 0; b = 1;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 1+0+1=10 sum is WRONG!");

              else

               $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 1+1+0=10 sum is WRONG!");

              else

               $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 1)

               $display(" 1+1+1=11 sum is WRONG!");

              else

               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);

  assign carry_out = a&carry_in|a&b|b&carry_in;

endmodule

一位元全加法器 結構模式(and.or.nor)

module top;

  integer ia,ib,ic;

  reg  a,b,c;

  wire cout,sum;

  mux_structural mux1(cout,sum,a,b,c);

  initial

    begin

      for (ic=0; ic<=1; ic = ic+1)

        begin

          c = ic;

          for (ia=0; ia<=1; ia = ia + 1)

            begin

              a = ia;

              for (ib=0; ib<=1; ib = ib + 1)

               begin

                 b = ib;

                 #1 $display("c=%d a=%d b=%d  cout=%d sum=%d",a,b,c,cout,sum);

               end

            end

        end

    end

endmodule

module mux_structural(cout, sum, A, B, cin);

 output cout, sum;

 input A,B,cin;

 xor x1(x, A, B);

 xor x2(sum,x,cin);

 and a1(y, A, B);

 and a2(z, cin, x);

 or  o1(cout, y, z);

endmodule

2015.11.4

     

一位元

二位元

module top7;

  integer ia0, ia1, ib0, ib1, is;

  reg  a0, a1, b0, b1, s;

  wire out1, out2;

  mux_behavioral mux1(out1, out2, a0, a1, b0, b1, s);

  initial

    begin

      for (is=0; is<=1; is = is+1)

        begin

          s = is;

          for (ia0=0; ia0<=1; ia0 = ia0 + 1)

            begin

              a0 = ia0;

              for (ia1=0; ia1<=1; ia1 = ia1 + 1)

               begin

                 a1 = ia1;

for (ib0=0; ib0<=1; ib0 = ib0 + 1)

              begin

                  b0 = ib0;

for (ib1=0; ib1<=1; ib1 = ib1 + 1)

                 begin

                   b1 = ib1;

                 #20 $display("a0=%d a1=%d b0=%d b1=%d s=%d out1=%d out2=%d",a0,a1,b0,b1,s,out1,out2);

               end

            end

        end

     end

  end

end

endmodule

module mux_behavioral(OUT1, OUT2, A0, A1, B0, B1, SEL);

 output OUT1,OUT2;

 input A0, A1, B0, B1, SEL;

 wire  A0, A1, B0, B1, SEL;

 reg    OUT1, OUT2;

  always @(A0 or A1 or B0 or B1 or SEL)

   OUT1 = (A0 & ~SEL)|(B0 & SEL );

   OUT2 = (A1 & ~SEL)|(B1 & SEL );

endmodule

2015.10.28

4位元多工器(and/or/not)

4位元(and/or/not)-程式碼

2位元(1位元+1位元)

二位元程式碼(一位元+一位元)

三位元(1位元+1位元+1位元)

三位元程式碼(1位元+1位元+1位元)

四位元(2+2)

四位元程式碼(2+2)

module HW6; 

wire [3:0] A, B, OUT;

wire SEL;

system_clock #25600 clock1(SEL);

system_clock #12800 clock2(A[3]);

system_clock #6400  clock3(A[2]);

system_clock #3200  clock4(A[1]);

system_clock #1600  clock5(A[0]);

system_clock #800   clock6(B[3]);

system_clock #400   clock7(B[2]);

system_clock #200   clock8(B[1]);

system_clock #100   clock9(B[0]);

mux2 mux_1(OUT[3:2], A[3:2], B[3:2], SEL);

mux2 mux_0(OUT[1:0], A[1;0], B[1:0], SEL);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>30000)$stop; 

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule 

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

三位元(1+2位元)

三位元程式碼(1+2位元)

module HW6; 

wire [2:0] A, B, OUT;

wire SEL;

system_clock #6400 clock1(SEL);

system_clock #3200 clock2(A[2]);

system_clock #1600 clock3(A[1]);

system_clock #800  clock4(A[0]);

system_clock #400  clock5(B[2]);

system_clock #200  clock6(B[1]);

system_clock #100  clock7(B[0]);

mux mux_1(OUT[2], A[2], B[2], SEL);

mux2 mux_0(OUT[1:0], A[1;0], B[1:0], SEL);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>30000)$stop; 

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule 

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

2015.10.21

2015.10.14

今天只弄出真值表

下次繼續完成

10/21(補)

圖