2015.11.18

一位元全加法器.行為模式

module test_adder1;

 reg a,b;

 reg carry_in;

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial

  begin

    carry_in = 0; a = 0; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 0)

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 0+1+0=01 sum is WRONG!");

              else

               $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 0)

               $display(" 0+1+1=10 sum is WRONG!");

              else

               $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 1+0+0=01 sum is WRONG!");

              else

               $display(" 1+0+0=01 sum is RIGHT!");

    carry_in = 1; a = 0; b = 1;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 1+0+1=10 sum is WRONG!");

              else

               $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 1+1+0=10 sum is WRONG!");

              else

               $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 1)

               $display(" 1+1+1=11 sum is WRONG!");

              else

               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);

  assign carry_out = a&carry_in|a&b|b&carry_in;

endmodule

一位元全加法器 結構模式(and.or.nor)

module top;

  integer ia,ib,ic;

  reg  a,b,c;

  wire cout,sum;

  mux_structural mux1(cout,sum,a,b,c);

  initial

    begin

      for (ic=0; ic<=1; ic = ic+1)

        begin

          c = ic;

          for (ia=0; ia<=1; ia = ia + 1)

            begin

              a = ia;

              for (ib=0; ib<=1; ib = ib + 1)

               begin

                 b = ib;

                 #1 $display("c=%d a=%d b=%d  cout=%d sum=%d",a,b,c,cout,sum);

               end

            end

        end

    end

endmodule

module mux_structural(cout, sum, A, B, cin);

 output cout, sum;

 input A,B,cin;

 xor x1(x, A, B);

 xor x2(sum,x,cin);

 and a1(y, A, B);

 and a2(z, cin, x);

 or  o1(cout, y, z);

endmodule