2015.11.25

三位元行結構模式

module adder1(cout, sum, A, B, cin);

 wire x,y,z;

 output cout, sum;

 input A,B,cin;

 xor x1(x, A, B);

 xor x2(sum,x,cin);

 and a1(y, A, B);

 and a2(z, cin, x);

 xor  o1(cout, y, z);

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

adder1 a1(sum[0], c[1], a[0], b[0], c_in) ;

adder1 a2(sum[1], c[2], a[1], b[1], c[1]) ;

adder1 a3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

module adder1(cout, sum, A, B, cin);

 wire x,y,z;

 output cout, sum;

 input A,B,cin;

 xor x1(x, A, B);

 xor x2(sum,x,cin);

 and a1(y, A, B);

 and a2(z, cin, x);

 xor  o1(cout, y, z);

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

adder1 a1(sum[0], c[1], a[0], b[0], c_in) ;

adder1 a2(sum[1], c[2], a[1], b[1], c[1]) ;

adder1 a3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule